1. Field of the Invention
The present invention relates to a substrate for a probe card used to test a plurality of semiconductor ICs (Integrated Circuits) in a lump.
2. Description of the Background Art
Referring to FIGS. 1 and 2, a conventional substrate for a probe card, generally designated with a reference numeral 1, is used to test a plurality of identical, semiconductor ICs (IC devices hereinafter) 2 formed on a wafer collectively. The probe card 1 includes a substrate 3 formed with a plurality of positioning holes 4. The positioning holes 4 are adapted to receive pins studded on a prober, not shown, to thereby position the probe card 1. The substrate 3 has tester terminals 5 formed thereon and connected to the test head of a tester, not shown, in order to transmit signals to and from the tester.
The substrate 3 includes a stack of layers 6, each of which has a particular pattern of electrically conductive material formed thereon. Those layers are referred to as signal layers. Those conductive patterns connect the tester terminals 5 to signal terminals 7 also formed on the substrate 3. Probe needles 9 for signals each are soldered or otherwise affixed to a particular needle seat portion 8 assigned to a signal. The needle seat portion 8 functions as transferring a signal from the signal terminal 7 to the probe needle 9. Each probe needle 9 includes a portion 9a covered with electrically insulative film and a contact portion 9b. The contact portion 9b has its tip contacting a pad positioned on associated one of the IC devices 2. In this condition, each probe needle 9 transfers a signal output from the tester to the associated IC device 2 and vice versa.
The substrate 3 has tester power supply terminals 10 formed thereon and connected to the tester head, so that a power supply voltage can be fed from the tester to the IC devices 2. The substrate 3 also includes an electrically conductive plate 11, which is divided into segments corresponding in number to the IC devices 2. In the specific, illustrative configuration, the conductive plate 11 is divided into eight segments in accordance with the number of IC devices 2 to be tested at the same time. The segments of the conductive plate 11 each connect the tester power supply terminals 10 to particular power supply terminals 12, which are arrayed on both sides of the test portion of the substrate 3, as seen in plan view of FIG. 1. The top and bottom surfaces in FIG. 2 of the conductive plate 11 are electrically insulated, so that the conductive plate 11 forms a power supply layer.
Further, probe needles 14 each are soldered or otherwise affixed to a particular needle seat portion 13 assigned to power supply. The needle seat portion 13 transfers an input voltage from the power supply terminal 12 to the probe needle 14. The probe needle 14 includes a portion 14a covered with electrically insulative film and a contact portion 14b. The contact portion 14b has its tip contacting a power supply pad 15 positioned on associated one of the IC devices 2, feeding a voltage input from the tester head to the probe needle 14. To the substrate 3, affixed is a probe holder 16 formed of a soft material. The probe needles 14 are inserted in the probe holder 16 and positioned thereby.
To test the IC devices 2 formed on the wafer in one lot, i.e. simultaneously, the probe needles 9 and 14 for signals and power supply are respectively brought into contact with the pads for signals, not shown, and the pads 15 for power supply, FIG. 1, of the IC devices 2. In this condition, a power supply voltage fed from the test head is received by the tester power supply terminals 10. The power supply voltage is then delivered from the power supply terminals 10 to the probe needles 14 via the conductive plate 11, power supply terminals 12, and needle seat portions 13. Finally, the power supply voltage is input to the IC devices 2 via the tips of the contact portions 14b contacting the power supply pads 15 of the IC devices 2.
Subsequently, a test signal is fed from the tester head to each IC device 2 via the associated tester terminal 5 for a signal, the conductive pattern provided on the associated signal layer 6, the signal terminal 7, the needle seat portion 8, the probe needle 9, and the signal pad of the IC device 2. The tester will then measure, e.g., a response time from sending the test signal to receiving a signal in response from the individual IC devices to determine whether or not the individual device are acceptable.
A current trend in the semiconductors art is toward the integration of many different kinds of devices including a memory and a CPU (Central Processing Unit) into a single IC device. This kind of IC device generally needs two or more different power supply voltages. FIG. 3 shows another conventional substrate for a probe card used to test such an IC device. In the figures, the same reference numerals designate the like elements. As shown, the probe card 1 is configured to test four IC devices 2 collectively, which are half as many as the IC devices 2 exemplarily shown in FIG. 1. A particular power supply voltage is applied to each of the upper and lower segments in the figure of the segmented conductive plate 11. In this condition, the tester, not shown, tests the individual IC devices 2 via the probe card 1 with different power voltages supplied.
FIGS. 4 and 5 show still another conventional substrate for a probe card. As shown, the probe card 1 is configured to test eight IC devices at a time, like the probe card 1 shown in FIG. 1. In this specific configuration, the conductive plate 11 is divided into sixteen segments, which are two times as many as the IC devices 2. A particular power supply voltage is applied to each of the right and left segments in FIG. 5 of the segmented conductive plate 11 via the power supply terminals 10 to thereby test the individual IC devices 2. As shown in FIG. 6, the probe card 1 can test even sixteen IC devices 2 simultaneously when the IC devices 2 are of the type fed with only a single power supply voltage.
The conventional probe cards 1 described above have the following problems left unsolved because they have only a single power supply layer each. When two different power supply voltages are necessary, use must be made of longer probe needles 14, as shown in FIG. 3. An increase in the length of each probe needle 14 directly translates into an increase in resistance and therefore in noise. This, coupled with a delay in response, makes the result of the test inaccurate and thereby reduces the number of accepted IC devices, decreasing the overall yield of IC devices. Moreover, it is likely that even acceptable IC devices are rejected.
Whereas the probe card 1 shown in FIG. 4 may solve the problem stated above, it needs a substitute substrate machined that would increase the test cost. Further, the substitute substrate needs a long production time and therefore lacks in adaptability. Moreover, when three or more different power supply voltages are required, the probe needles 14 must also be as long as the probe needles 14 shown in FIG. 3, reducing the yield of IC devices.
In an application where the same power supply voltage must be applied to two portions of each IC device to be tested, and an application where the same power supply voltage is fed from a left and a right conductive plate to the IC device via, e.g., the probe needle arrangement of FIG. 4 for promoting a wide use, any little difference between power supply voltages input to the two conductive plates would make the result of the test erroneous. To solve this problem, it was necessary to feed the power supply voltage from a single conductive plate as in the configuration shown in FIG. 1. It follows that a widely usable probe card adaptive to various kinds of IC devices with a single substrate was difficult to achieve.
It is an object of the present invention to provide a widely usable substrate for a probe card readily adaptive to various kinds of power supply voltages and various kinds of semiconductor IC devices with a single substrate.
A substrate for a probe card of the present invention includes a plurality of tester power supply terminals which receive a power supply voltage output from a tester. A plurality of power supply terminals are connected to a semiconductor IC device to be tested. At least two power supply layers each connect one of the tester power supply terminals to the power supply terminals.